| 题名: | Research on serial ATA hard disk initialization |
| 作者: | WEi Wu; Haibing Su; Qinzhang Wu
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| 出版日期: | 2009
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| 会议名称: | 2009 International Workshop on Intelligent Systems and Applications
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| 会议日期: | 2009
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| 通讯作者: | WEi Wu
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| 中文摘要: | Serial ATA (SATA) is the successor of the Parallel ATA (PATA) interface. SATA overcomes many limitations of PATA and offers a maximum bandwidth of 300 MB/s. The Virtex-4 embedded multi-gigabit transcEiver (MGT) is compatible with SATA protocol. Combining MGT with the flexible configurable logic fabric and many specialized high-performance embedded features, Virtex-4 FPGA is an ideal single-chip solution for embedded SATA application. This paper presents how to implements SATA physical link initialization in Virtex-4 FPGA through the use of Out-of-Band (OOB) signals to synchronize and reset SATA hard disk. Dynamically changing attributes of MGT via the Dynamic Reconfiguration Port (DRP) is employed to improving usability and performance of the design. The whole design is validated on the Xilinx ML405 evaluation platform connecting to a SATA hard disk. The experiment results show that the design can complete SATA physical link initialization and establish communication link between SATA host controller in FPGA and hard disk. |
| 英文摘要: | Serial ATA (SATA) is the successor of the Parallel ATA (PATA) interface. SATA overcomes many limitations of PATA and offers a maximum bandwidth of 300 MB/s. The Virtex-4 embedded multi-gigabit transcEiver (MGT) is compatible with SATA protocol. Combining MGT with the flexible configurable logic fabric and many specialized high-performance embedded features, Virtex-4 FPGA is an ideal single-chip solution for embedded SATA application. This paper presents how to implements SATA physical link initialization in Virtex-4 FPGA through the use of Out-of-Band (OOB) signals to synchronize and reset SATA hard disk. Dynamically changing attributes of MGT via the Dynamic Reconfiguration Port (DRP) is employed to improving usability and performance of the design. The whole design is validated on the Xilinx ML405 evaluation platform connecting to a SATA hard disk. The experiment results show that the design can complete SATA physical link initialization and establish communication link between SATA host controller in FPGA and hard disk. |
| 收录类别: | Ei
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| 语种: | 英语
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| 文章类型: | 会议论文
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| 页码: | 896-
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| 内容类型: | 会议论文
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| URI标识: | http://ir.ioe.ac.cn/handle/181551/7509
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| Appears in Collections: | 光电探测技术研究室（三室）_会议论文
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| 2009-178.pdf（314KB） | 会议论文 | -- | 限制开放 | | View
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| Recommended Citation: | |
WEi Wu,Haibing Su,Qinzhang Wu. Research on serial ATA hard disk initialization[C]. 见:2009 International Workshop on Intelligent Systems and Applications. 2009.
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