IOE OpenIR  > 光电技术研究所博硕士论文
基于FPGA的H.264帧内编码器并行硬件结构的研究
Alternative TitleResearch of Parallel Hardware Architecture for H.264 Intra Encoder Based on FPGA
张刚
Subtype硕士
Thesis Advisor苏海冰
2009-05-25
Degree Grantor中国科学院光电技术研究所
Place of Conferral光电技术研究所
Degree Discipline信号与信息处理
Keyword图像压缩 H.264 可编程逻辑器件 帧内编码器 并行
AbstractH.264作为最新的视频压缩编解码标准,采用了许多先进的技术来进一步提高图像的压缩效率,其应用前景非常广阔。现在,世界上很多科研机构和公司都投入了对H.264的研究和开发。由于H.264编码算法复杂度很高,软件实现难以满足高分辨率图像的实时压缩,所以需要设计硬件编码器。 本文设计了一种并行的用于高分辨率图像压缩的H.264帧内编码器的硬件结构。并在FPGA上实现了宏块从预测到重建的环形处理流程,最后对设计进行了仿真和验证。针对H.264帧内编码器硬件实现方面的困难,我们提出了其硬件设计的具体解决方案:由于亮度分量的帧内预测方式多达13种,通过分析各预测公式的特点,我们提出了一种共享加法项的设计方法,可以同时得到所有预测方式的预测值。模式判断模块采用了4x4子块级的流水线结构,既避免了构造大型的减法网络,又提高了处理速度。为了减少宏块从预测到重建的处理时间,我们同时设计了一种高并行度的二维整数DCT/DHT变换结构,在两个相邻的时钟周期内就可以得到一个4x4子块的16个变换结果,量化模块根据变换模块的硬件结构,设计了由8个基本量化单元组成的并行处理结构。 为了验证FPGA设计部分功能的正确性,我们把CAVLC编码在DSP上进行移植。DSP读取FPGA产生的量化结果,产生编码比特流,最后通过软件解码来验证帧内编码器设计的正确性。最后的实验结果表明,FPGA部分的设计与软件参考模型的结果完全一致,可以达到实时处理1Kx1K 30fps视频图像的能力。
Other AbstractAs the latest video compression codec standard, H.264 introduces many advanced techniques to further improve image compression efficiency. It has very broad application prospect. Now, there are a lot of research institutions and companies researching and developing H.264 all over the world. The H.264 coding algorithm is so complexity that the software implementation can't meet the real-time compression of high-resolution image, so it’s necessary to design the hardware encoder for H.264. In this paper, the intra encoder with a parallel hardware architecture of H.264 has been designed for the application of high-resolution image compression, and the annular processing of macroblock from prediction to reconstruction has been implemented on FPGA. At last, the simulation and verification of intra encoder is accomplished. A specific solution has been proposed to solve the difficulties of hardware implementation for intra encoder. Because there are 13 different kinds of intra prediction modes for the luminance component, a method of sharing the same adder cells has been proposed through the analysis of the characteristics of the prediction formulae. All of the prediction values can be obtained at the same time.In mode decision module,a 4x4 sub-macroblock level pipeline architecture has been proposed, which avoids constructing the large-scale network of subtraction,but also improves the proccessing speed. In order to reduce the time of the macroblock's processing, a high-parallel 2-D integral DCT/DHT transform architecture has been designed. 16 transform results of a 4x4 sub-macroblock can be obtained wihtin two adjacent clock cycles. Based on the hardware architecture of transform model, a parallel processing architecture with eight basic quantization cells in quantization module is proposed. In order to verify the correctness of the FPGA's function, the CAVLC coding is transplanted on DSP. The quantization results from FPGA are encoded by DSP, and then the bitstream is decoded by software model to verify its correctness. The final experimental results show that the result of FPGA is exactly the same as the software model, and it can fully satisfy the constraint of real-time processing required by 1Kx1K 30fps video.
Pages77
Language中文
Document Type学位论文
Identifierhttp://ir.ioe.ac.cn/handle/181551/380
Collection光电技术研究所博硕士论文
Recommended Citation
GB/T 7714
张刚. 基于FPGA的H.264帧内编码器并行硬件结构的研究[D]. 光电技术研究所. 中国科学院光电技术研究所,2009.
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