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题名:
基于FPGA的二维离散提升小波变换IP核设计
作者: 欧龙
学位类别: 硕士
答辩日期: 2008-06-04
授予单位: 中国科学院光电技术研究所
授予地点: 光电技术研究所
导师: 杨洪
关键词: 二维离散提升小波变换 ; IP核设计 ; FPGA ; CSD编码乘法器 ; testbench
其他题名: IP Core design of 2-D lifting-based DWT based on FPGA
学位专业: 检测技术与自动化装置
中文摘要: 小波变换是时间-尺度分析和多分辨率分析的一种新技术,其中提升小波变换具有许多优良的特性,它在信号分析、图像处理等多领域都取得了广泛的应用成果。而IP核的设计与复用技术是SOPC设计的核心,所以设计高性能可重用的二维离散提升小波变换IP核有重要的工程实用价值。 论文首先研究了基于FPGA的可重用设计方法学、IP核设计技术以及规范,在参考业界IP设计技术的基础上,对IP核设计流程、代码风格、验证策略、交付文档规范等作了较详细的总结,从而为论文的二维离散提升小波IP核设计提供了指导。 其次,详细研究了Daubechies(9,7)小波的硬件实现。通过Matlab仿真,确定了小波变换数据通道上的数据精度;通过分析二维小波变换的数据流,提出了一种高效并行的二维离散提升小波变换结构,该结构只需要7行数据缓存,即可实现行和列方向同时进行滤波变换,极大地减少了存储器资源的占用;采用了内嵌的边界延拓算法,节约了存储器资源,并且减少了处理时间;小波变换的常系数乘法器用基于CSD编码和优化的“移位加/减”操作来实现,并且插入多级流水线结构,提高了处理速度。 最后用VHDL设计可自动验证的testbench,通过Matlab+Modelsim联合仿真能方便有效地对IP核进行验证。此IP核具有3个可配置参数,分别为图像尺寸、位宽、小波变换的级数,可方便重用。该IP核已经在XC2VP20 FPGA上实现,并能稳定工作在60MHz时钟频率下,其处理512 512 8bit图像的速度可达240fps,完全满足高速图像实时处理的要求。
英文摘要: Wavelet transform is a new technology of multi-resolution analysis. Lifting-based discrete wavelet transform (DWT) has many good traits, so it is successfully used in many different fields, including signal analyzing, image processing. IP Core design and reuse are the key of SOPC, which become the trend of system design. So that, designing the high-performance and reuseable IP Core of 2D-lifting-based discrete wavelet transform is useful for engineering application. First of all, this paper makes a study of the reuse methodology based on FPGA, and the standard of IP Core design technology. The standards of design flow, coding style, the strategy of verification, and the document of IP Core design are summarized in detail according to the technology of some EDA companies and organizations. Consequently it is a guideline of this paper’s IP Core design. Secondly, this paper designs the hardware architecture of Daubechies(9,7) wavelet. The best hardware bit-width is given according to simulation by Matlab. An embed architecture of boundary extension is given saving hardware resource and reducing processing time. A CSD coding-based and optimized “shift-add/sub” operations are adopted to implement multiplier with a constant coefficient. Multiple pipeline registers are inserted to the architecture to increase the processing speed. A highly efficient, parallel pipelined architecture is proposed for 2D-lifting-based discrete wavelet transform. The architecture can process both the row transform and column transform concurrently via just seven-line buffers. Based on Matlab and Modelsim, the IP core can be self-verified efficiently and conveniently via the testbench coded by VHDL. The IP core with three configurable parameters which are the size, the bit-width, the level of wavelet, can be reused conveniently. It had been verified at 60MHz clock frequency on XC2VP20 FPGA. It can process 240-frame images of 512 512 8bit per second, meeting the request for real time processing of high-peed image.
语种: 中文
内容类型: 学位论文
URI标识: http://ir.ioe.ac.cn/handle/181551/333
Appears in Collections:光电技术研究所博硕士论文_学位论文

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Recommended Citation:
欧龙. 基于FPGA的二维离散提升小波变换IP核设计[D]. 光电技术研究所. 中国科学院光电技术研究所. 2008.
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