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题名:
基于脉动阵列的实时波前处理机原理验证
作者: 唐端午
学位类别: 硕士
答辩日期: 2008-06-06
授予单位: 中国科学院光电技术研究所
授予地点: 光电技术研究所
导师: 王春鸿
关键词: 自适应光学 ; 波前处理机 ; 脉动阵列 ; FPGA ; 有限字长效应
其他题名: The Principle Demonstration of Real-time Wave-front Processor Based on Systolic Array
学位专业: 信号与信息处理
中文摘要: 波前处理机的主要技术难点是运算量大和实时性要求严格。随着自适应光学技术的发展,系统的单元数越来越多,波前传感器的采样频率不断提高,使得普通的von Neumann型计算机系统的运算能力难以满足要求。同时系统对波前处理机的集成度、通用性等方面也提出了更高的要求。因此,研制综合性能更强的波前处理机,对自适应光学技术的发展具有重要意义。 脉动阵列机是一种适合于波前处理运算特点的并行计算机。为了对基于脉动阵列的波前处理机原理进行验证,本文设计了基于这种结构的61单元自适应光学系统波前处理平台。该平台由三个脉动阵列构成,以流水线的方式分别进行斜率运算、复原运算和控制运算。在这三个阵列内部,又分别采用流水处理和并行处理相结合的办法,将各阵列的任务划分成一系列基本的子过程,实现了操作级的并行,从而提高了流水线处理机的吞吐率。对阵列与阵列之间、各阵列内部数据信号和控制信号的时序进行了分析,分别针对各部分的运算特点设计全局和局部的时序控制电路,从而优化了处理机的时序控制。在FPGA上采用定点运算方式实现波前控制运算,量化字长的确定是一个关键技术难点。本文对数字控制器的有限字长效应进行了分析。首先分析了系数的量化对控制器稳定性的影响,用MATLAB计算出了不影响控制器性能的系数量化字长;然后对运算过程中的量化噪声建立了统计模型,推导出了满足运算结果精度需要的乘法结果量化字长,为程序设计过程中字长的选择提供了理论基础。波前处理机在一片Xilinx XC2V3000 FPGA上实现。最后,针对61单元的自适应光学系统在波前处理机实验平台上进行了实验研究,测量出了各模块的运算延时。结果表明,该波前处理机对一帧图像的运算延时仅为9.2μs。 该波前处理机完全采用标准的VHDL语言开发,只需要修改程序代码便可以满足不同应用背景的需要,可移植性好,完全能够满足下一代自适应光学系统对波前处理机灵活性和通用性等方面的要求。
英文摘要: The main technologic difficulties of the Adaptive Optics (AO) wave-front processor are large amounts of calculations and low latency requirement. With development of AO technology, more sub-apertures and higher sample rates of the wave-front sensor are necessary, which poses a significant challenge to von Neumann architecture processors system. The processor is also required to be high integrating and general-purpose. Consequentially, it is significant to develop wave-front processors with highly comprehensive performances. The systolic array processor is a parallel processor which is suitable for wave-front operations. In order to validate the principle of the wave-front processor based on systolic array, a 61-element AO wave-front process platform which is composed of three systolic arrars is designed. The three arrays work in a pipeline to accomplish slope calculation, wave-front reconstruction and control algorithm. In each of the array, the task is disassembled into a series of basic sub-procedure by pipeline and parallel processing technology to realize operation class parallelism,then the throughput rate of the pipeline processor increases greatly. In order to optimize timing control, timing of data and control signals which are between or in systolic arrays is analyzed and global and local timing control circuits are designed according to characteristic of the operation. Quantized word length determination is a technologic difficulty when using fix-point arithmetic to accomplish wave-front control algorithm based on FPGA. The finite word length effect of the digital controller is analyzed in this paper. The influence to the stability and system performance of the controller is analyzed and word length quantizing coefficients that meeting the demand of the controller is calculated by MATLAB. Statistic model of the round-off noise during the operation is established and a formula which calculates the word length of the word length quantizing the multiplicative results that meet the precision required by the system is developed. The processor is implemented on a Xilinx XC2V3000 FPGA. Finally, the experiment is performed on the hardware platform according to the 61-elment AO system and process delay of each systolic array is measured. Experimental results show that process delay of the wave-front processor is only 9.2μs. The processor is developed with VHDL. When application background changed, it is only need to modify the code,Therefore, the processor which is flexible and general purpose can meet the demand of next AO system.
语种: 中文
内容类型: 学位论文
URI标识: http://ir.ioe.ac.cn/handle/181551/327
Appears in Collections:光电技术研究所博硕士论文_学位论文

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Recommended Citation:
唐端午. 基于脉动阵列的实时波前处理机原理验证[D]. 光电技术研究所. 中国科学院光电技术研究所. 2008.
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